Behavior to Structure: Using Verilog and In-Circuit Emulation to Teach How an Algorithm Becomes Hard - Verilog HDL Conference, 1995. Proceedings., 1995 IEEE International

W e present three stages of Verilog simulation (pure behavioral, mixed behavioral/structural, and pure structural), and a final stage of In-Circuit Emulation for translating an algorithm into hardware. Each successive stage i n the translation can be derived by minor editing of the previous stage. The pure behavioral stage uses a single Verilog process to model an algori thmic state machine (ASM) using statements such as while and non-blocking assignment. The mixed stage keeps the algorithm i n a readable f o r m using statements such as while, but replaces the non-blocking assignment with a structural "architecture" that manipulates data. T h e third stage replaces statements such as while with a simulation of a conventional structural controller that generates the next state. The f i nal stage involves synthesizing actual hardware for the controller, and interfacing it t o the Verilog simulation of the architecture using an MS-DOS device driver that works in cooperation with a special module in VeriWe1 1/PC.